1. Field
Embodiments of the invention relate to electronic systems, and more particularly, to synchronization of phase-locked loops (PLLs).
2. Description of the Related Technology
Phase-locked loops (PLLs) can be used in a variety of applications for generating an output clock signal having a controlled phase and frequency relationship to a reference clock signal. PLLs can be used in, for example, telecommunications systems and/or chip-to-chip communication.
An integer-N frequency synthesizer can be implemented using a PLL having an integer frequency divider inserted in the PLL's feedback loop. The integer-N frequency synthesizer can be used to synthesize output frequencies in steps of a reference frequency by selecting an integer division value N of the frequency divider. For example, at steady state, the frequency of the synthesizer's output clock signal should be N times the reference clock signal's frequency. Additionally, in an integer-N frequency synthesizer, at steady state the output clock signal should have N periods for every period of the reference clock signal. Therefore, a rising edge of the reference clock signal can be synchronized with a rising edge of the output clock signal.
To provide finer steps of output frequency adjustment, a fractional-N synthesizer can be used. In contrast to an integer-N frequency synthesizer that uses integer division values, a fractional-N synthesizer permits fractional division values. At steady state, the frequency of the synthesizer's output clock signal should be N+F/M times the reference clock signal's frequency, where N is the integer portion of the division value and F/M is the fractional portion of the division value.
In certain configurations, an interpolator can be used to generate the fractional portion of the division value. For example, the output of the interpolator can include a sequence of integer division values with an average value given by F/M, where F is the numerator of the fractional portion and M is the denominator of the fractional portion.